Bias network for high efficiency RF linear power amplifier

ABSTRACT

A bias network uses resistive biasing, active biasing and current mirror biasing in combination to enhance RF power amplifier linearity and efficiency by forming a bias network that provides temperature compensation, minimizes current drain requirements for the Vbias source and reduces the level of RF linear amplifier quiescent current.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates generally to radio frequency (RF)linear power amplifier bias networks and, more particularly, to a biasnetwork for minimizing distortion products normally associated withbipolar transistor based RF power amplifiers.

[0003] 2. Description of the Prior Art

[0004] An important goal associated with design of bipolar transistorbased linear amplifiers includes minimizing the introduction ofdistortion products. It is known that load impedance can be optimizedfor minimum distortion. Optimization of just the load impedance,however, is often undesirable since the output power and efficiencygenerally are reduced. It is also known that any bias network mustsupply the correct amount of bipolar transistor base current to preventor minimize distortion. Two trends associated with bipolar transistorbase current must be reconciled to produce a linear amplifier withminimum amplitude modulation (AM) distortion, e.g. AM-to-AM. Forexample, the bias current required by a bipolar transistor in class Boperation increases as the square root of the power. Further, the basecurrent, and thus the collector current increases exponentially withincreasing base-emitter voltage. Any reduction in distortion productswill allow a linear amplifier to be operated closer to saturation,thereby improving the efficiency.

[0005] When a linear amplifier bias point is chosen very close to aclass B mode, efficiency can be improved. This condition, however,places a heavy demand on the associated bias network to supply a largerange of bias currents as the linear amplifier power requirements vary.Two approaches have been used in the art to provide the requisite biasnetwork. First, a resistive bias network has been used where the basecurrent is supplied through a bias resistor. Second, an active biasnetwork has been used where an emitter follower transistor is used toprovide a low impedance bias supply. The resistive bias approachprovides limited bias current control over power. For example, if theresistor is small, temperature variations will cause unacceptablefluctuations in the quiescent current unless the bias network supplyvoltage also changes with temperature. If the resistor is large, thelinear amplifier will be have insufficient bias current at high drivelevels or have a large quiescent bias current which is undesirable. Theactive bias network allows an RF device to draw varying amounts of biascurrent depending upon the RF drive while maintaining a low quiescentlevel. The foregoing bias networks, therefore, can affect the linearityof an RF amplifier.

[0006] As stated above, one measure of linearity is AM-to-AM distortiondue to RF amplifier gain changes that occur as the RF amplifier powerlevel changes. The gain of an amplifier with resistive biasing willdecrease as the power increases since the bias resistor will not passthe increased base current. Amplifiers with active biasing, however,will exhibit gain expansion since the effective bias current willincrease at a larger rate than that required as the power is increased.This condition occurs because the average impedance looking back intothe emitter of the bias current supply transistor decreases as thecurrent increases.

[0007] In view of the above, a temperature compensated amplifierquiescent current is desirable since it helps maintain linearity andefficiency over the desired operating range of the amplifier. Onetechnique that has been used to produce temperature compensation at aspecific bias voltage includes a combination of resistive biasing andactive biasing referred to in the art as “buffered passive bias.” Thebuffered passive bias scheme reduces the current that must be suppliedby the bias network voltage source. Another technique that has oftenbeen used to produce temperature compensation includes a current mirrorbias network. The current mirror bias network provides bias currentcontrol over a wide temperature range, but requires higher levels ofcurrent from the bias network voltage source. In one case, thermalvariations in the amplifier output transistor quiescent current, whenusing a current mirror bias network, track current changes through acollector bias resistor as the base-emitter voltage associated with thecurrent mirror transistor and amplifier transistor change overtemperature. If the bias network voltage is large compared to thebase-emitter voltages, then the quiescent current will not change muchover temperature.

[0008] The above techniques, familiar to those skilled in the art oflinear amplifiers, affect the AM-to-AM linearity performance of theamplifier. As known in the art, amplifier performance limitations areaffected by impedance variations seen looking back into the bias and RFmatching networks. In one known embodiment, the amplifier outputtransistor collector current varies exponentially with its base-emittervoltage, as stated above. Therefore, a large RF impedance at theamplifier output transistor base is desirable for linearity since itwill behave more like a constant current source. Use of a large RFimpedance, however, is not desirable to achieve optimum energy transfer.One known technique that addresses the foregoing problems includessetting the value of an input RF coupling capacitor to the requisitevalue to achieve desired RF performance with the understanding that ahigher impedance (smaller capacitor value) will achieve betterlinearity.

[0009] In class B operation, one requirement placed upon the associatedbias network includes metering charge into an input RF couplingcapacitor on the negative portion of the RF cycle at a rate thatincreases as the square root of the RF power. This charge is then pumpedinto the amplifier transistor base during the positive portion of the RFcycle. As stated above, a factor in controlling amplifier linearity isthe impedance of the bias network. Other than the resistive biastechnique, known biasing techniques discussed above generally haveimpedances that are too low. This characteristic generally tends tosupply charge (current) to the input RF coupling capacitor discussedabove at a higher rate than needed as the power increases and thusproduces unwanted gain expansion. While the linearity performance of aresistive bias amplifier can be optimal, such techniques generallyrequire excessive bias current from the bias network voltage source.

[0010] Thus, there remains a need for a new and improved bias networksuitable for use with bipolar transistor power amplifiers and thateffectively minimizes distortion products to achieve optimum linearitywhile substantially preserving efficiency.

SUMMARY OF THE INVENTION

[0011] The present invention is directed to a bias network configured tocontrol AM-to-AM performance for a bipolar linear amplifier. Oneembodiment comprises a modified buffered passive bias network incombination with a modified current mirror bias network. The modifiedbuffered passive bias network provides temperature compensation andminimizes current drain requirements associated with the bias networkvoltage source. The modified current mirror aids in the temperaturecompensation and in reducing the level of bipolar linear amplifierquiescent current. The impedance of the modified buffered passive biasnetwork is adjusted through a conventional bias resistor in combinationwith an impedance adjusting resistor added to the emitter of the activebias transistor. The impedance of the modified current mirror biasnetwork is adjusted substantially via a resistor added to the base ofthe current mirror bias transistor and also to a lesser extent via aresistor added to the collector of the current mirror bias transistor.

[0012] Another embodiment comprises a modified buffered passive biasnetwork as described above in combination with a modified current mirrorbias network in which an inductor is added to the emitter of the currentmirror bias transistor.

[0013] Yet another embodiment comprises a modified buffered passive biasnetwork as described above in combination with a modified current mirrorbias network as also described above in which the bias network voltagesource is provided via a voltage drop across a plurality of diodes.

[0014] Still another embodiment comprises a modified buffered passivebias network as described above in combination with a modified currentmirror bias network as also described above in which the bias networkvoltage source is provided via a voltage drop across a plurality ofdiode connected transistors (base/collector connected) to provide atemperature variable reference voltage.

[0015] Another embodiment comprises a modified buffered passive biasnetwork as described above in combination with a modified current mirrorbias network as also described above in which the bias network voltagesource is provided via a voltage drop across at least one diodeconnected transistor in combination with one or more resistors toprovide a temperature variable reference voltage.

[0016] Another embodiment comprises a modified buffered passive biasnetwork as described above in which the bias network voltage source isprovided by a diode reference network as also described above.

[0017] Accordingly, one feature of the present invention includesprovision of a current bias network configured to minimize introductionof distortion products associated with a bipolar linear amplifier.

[0018] Another feature of the present invention includes provision of acurrent bias network configured to allow a bipolar linear amplifier tobe operated very close to saturation to improve amplifier efficiency.

[0019] Still another feature of the present invention includes provisionof a bipolar linear amplifier current bias network configured to providetemperature compensation and minimize current drain requirementsassociated with the current bias network.

[0020] Yet another feature of the present invention includes provisionof a bipolar linear amplifier current bias network configured to providetemperature compensation and reduce the level of quiescent current drainrequirements associated with the bipolar linear amplifier.

[0021] Still another feature of the present invention includes provisionof a current bias network that can be combined with a bipolar linearamplifier to produce a linear amplifier with minimum AM-to-AMdistortion.

[0022] These and other features of the present invention will becomeapparent to those skilled in the art after a reading of the followingdescription of the preferred embodiment when considered with thedrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0023]FIG. 1 is a schematic diagram illustrating a resistive biasnetwork known in the art

[0024]FIG. 2 is a schematic diagram illustrating an active bias networkknown in the art.

[0025]FIG. 3 is a schematic diagram illustrating a buffered passive biasnetwork known in the art.

[0026]FIG. 4 is a schematic diagram illustrating a current mirror biasnetwork known in the art.

[0027]FIG. 5 is a schematic diagram illustrating a modified active biasnetwork according to one embodiment of the present invention.

[0028]FIG. 6 is a schematic diagram illustrating a modified bufferedpassive bias network according to one embodiment of the presentinvention.

[0029]FIG. 7 is a schematic diagram illustrating a modified currentmirror bias network according to one embodiment of the presentinvention.

[0030]FIG. 8 is a schematic diagram illustrating another modifiedcurrent mirror bias network according to one embodiment of the presentinvention.

[0031]FIG. 9 is a schematic diagram illustrating a current bias networkaccording to one embodiment of the present invention.

[0032]FIG. 10 is a schematic diagram illustrating a current bias networkaccording to another embodiment of the present invention.

[0033]FIG. 11 is a schematic diagram illustrating another bias networkknown in the art.

[0034]FIG. 12 is a schematic diagram illustrating another modifiedcurrent bias network according to one embodiment of the presentinvention.

[0035]FIG. 13 is a schematic diagram illustrating a current bias networkaccording to anther embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0036] In the following descriptions, like reference charactersdesignate like or corresponding parts throughout the several views.Referring now to the drawings in general and FIG. 1 in particular, itwill be understood that the illustrations are for the purpose ofdescribing a preferred embodiment of the invention and are not intendedto limit the invention thereto. As shown in FIG. 1, a schematic diagramillustrates a resistive bias circuit 100 known in the art. The basecurrent to a transistor amplifier 102 is supplied through a biasresistor 104. This biasing approach provides limited bias currentcontrol over power. For example, if the bias resistor 104 is small,temperature variations can cause unacceptable fluctuations in thequiescent current associated with the transistor amplifier 102 unlessthe bias voltage Vbias 106 changes with temperature. If the biasresistor 104 is large, the transistor amplifier 102 will be bias starvedat high drive levels or otherwise have an undesirably large quiescentbias current.

[0037]FIG. 2 is a schematic diagram illustrating an active bias circuit200 known in the art. The active bias circuit 200 is an improvement overthe resistive bias circuit 100 shown in FIG. 1 since the active biascircuit 200 allows the associated transistor amplifier 102 to drawvarying amounts of bias current depending upon the radio frequency (RF)drive level while still maintaining a low quiescent current level. Theresistive bias circuit 100 and the active bias circuit 200 both affectthe transistor amplifier 102 linearity, e.g., AM-to-AM distortion, dueto transistor gain changes with changes in power level. For example,amplifier gain with resistive bias will decrease as the power levelincreases since the resistor 104 will not pass the increased basecurrent as stated above. Amplifiers having active biasing will exhibitgain expansion with increasing power levels. This is because theeffective bias current will increase at a larger rate than required dueto decreasing average impedance (variable impedance) associated with thebias current supply transistor 202 as the current increases.

[0038]FIG. 3 is a schematic diagram illustrating a buffered passive biascircuit 300 known in the art. As stated above, temperature compensationin the transistor amplifier 102 quiescent current is desirable since ithelps maintain linearity and efficiency over the operating range of theamplifier 102. The buffered passive bias circuit 300 combines aresistive bias circuit 100 with an active bias circuit 200 to produceimproved temperature compensation at a specific bias voltage. A featureof this active bias circuit 300 includes a reduction in current thatmust be supplied by the active bias circuit voltage source Vbias 302.

[0039]FIG. 4 is a schematic diagram illustrating a current mirror biascircuit 400 known in the art. The current mirror bias circuit 400provides excellent bias current control over a wide temperature range atthe expense of increased current requirements for the current mirrorbias circuit voltage source Vbias 402. In operation, the current mirrorbias transistor 404 quiescent current tracks the transistor amplifier102 quiescent current because of the common base-emitter voltage. If thevoltage drop across R1 is large compared to the thermal variation in thebase-emitter voltage (V_(BE)), the quiescent bias current will remainrelatively unchanged over temperature.

[0040]FIG. 5 is a schematic diagram illustrating a modified active biascircuit 500 according to one embodiment of the present invention. Asstated above, a factor in controlling the amplifier linearity is theimpedance of the bias network. The bias circuits illustrated in FIGS.2-4 have impedances that are too low for use in linear amplifierapplications. For example, a low impedance will tend to supply charge(current) to capacitor C1 as the power increases, thereby producing gainexpansion. The bias circuit illustrated in FIG. 1 could be optimum butfor the excessive bias current required from the bias voltage sourceVbias 106. The modified active bias circuit 500 includes a resistor R2added to the emitter of the active bias circuit transistor 202 to reduceor minimize any gain expansion produced by the modified active biascircuit 500. Preferably, resistor R2 is selected to achieve maximumlinearity and efficiency about a desired operating point for thetransistor amplifier 102.

[0041]FIG. 6 is a schematic diagram illustrating a modified bufferedpassive bias circuit 600 according to one embodiment of the presentinvention. The modified passive bias circuit 600 allows adjustments tothe bias impedance and a degree of temperature compensation viaresistors R2 and R3. Preferably, resistors R2 and R3 are adjusted tomaximize transistor amplifier 102 operating efficiency and linearitywith minimal quiescent bias current demands upon the bias circuitvoltage source 602.

[0042]FIG. 7 is a schematic diagram illustrating a modified currentmirror bias circuit 700 according to one embodiment of the presentinvention. The modified current mirror bias circuit 700 allowsadjustments to the bias impedance and a degree of temperaturecompensation via resistors R1, R2 and R3. For example, resistors R2 andR3 allow adjustments in the temperature compensation characteristicsassociated with the transistor amplifier 102 while resistors R1, R3 andto a lessor extent R2, all interact to affect the bias circuitimpedance. Preferably, resistors R1, R2 and R3 are adjusted to maximizelinearity and operating efficiency with minimal quiescent bias currentdemands upon the modified current mirror bias circuit voltage source702.

[0043]FIG. 8 is a schematic diagram illustrating another modifiedcurrent mirror bias circuit 800 according to one embodiment of thepresent invention. The impedance of the modified current mirror biascircuit 800 can be increased via addition of an inductor L1 to theemitter of the modified current mirror bias transistor 802. Chip area isimportant when using a monolithic power amplifier. Therefore, it ispreferable to provide a connection for use with an external inductorwhen the modified current mirror bias circuit 800 is used in associationwith a monolithic power amplifier.

[0044]FIG. 9 is a schematic diagram illustrating a bias network 900according to one preferred embodiment of the present invention. The biasnetwork 900 has a modified buffered passive circuit 902 and a modifiedcurrent mirror bias circuit 904. The modified buffered passive biascircuit 902 provides a predetermined amount of temperature compensationwhile attributing to minimization of current drain requirementsassociated with the bias circuit voltage source Vbias 906. The modifiedcurrent mirror bias circuit 904 aids in the temperature compensation andin reducing the level of quiescent current associated with thetransistor amplifier 102. The impedance of the bias network 900 isadjusted through resistors R2, R3, R4 and to a lessor extent resistorR5. The resistor R6 generally provides bias ballast for the transistoramplifier 102 and is typically too small to provide linearityimprovements when used in association with the bias network 900. Thebias network 900 allows greater flexibility than known bias circuits inproviding a bias current source capable of achieving design constraintsnecessary to create a linear amplifier having superior AM-to-AMperformance and temperature compensation.

[0045]FIG. 10 is a schematic diagram illustrating another bias network1000 according to another embodiment of the present invention. The biasnetwork 1000 is similar to the bias network 900 illustrated in FIG. 9,except the bias voltage source Vbias 1002 is combined with a pair ofdiode connected transistors 1004 to generate a desired bias voltage onthe integrated circuit (IC) chip. This embodiment is not so limitedhowever, and it shall be understood that a desired bias voltage can alsobe generated by replacing the pair of diode connected transistors 1004with a single transistor, one or more diodes, or combinations thereof.One or more resistors can also be combined with the transistor(s) and/ordiode(s) to more particularly refine the desired bias voltagecharacteristics.

[0046]FIG. 11 is a schematic diagram illustrating a buffered passivebias circuit 1100 that is known in the art. The bias circuit 1100 usestwo diode connected transistors 1102 to provide a temperature variablereference voltage. Other implementations of the bias circuit 1100 knownin the art employ a single transistor in combination with a resistor toprovide a reference voltage. As stated above, a classic buffered passivebias circuit such as circuit 1100 tends to produce undesirable gainexpansion under some circumstance when used to bias a linear amplifier.One embodiment of the present invention minimizes undesirable gainexpansion by adding a properly sized resistor to the emitter of theactive transistor associated with the buffered passive bias circuit suchas illustrated in FIGS. 5 and 6. The newly added emitter resistoroperates to improve linearity by strategically maximizing the biascircuit impedance at a desired operating point.

[0047]FIG. 12 is a schematic diagram illustrating a modified bufferedpassive bias circuit 1200 according to one embodiment of the presentinvention. The bias circuit 1200 is like the bias circuit 1100 shown inFIG. 11, except an additional impedance adjustment resistor 1202 isadded to the emitter of the bias circuit transistor 1204 to improvelinearity by minimizing gain expansion as stated above. Although themodified buffered passive bias circuit 1200 is an improvement overclassic buffered passive bias schemes known in the art, a more preferredscheme uses any of the bias networks shown in FIGS. 9 and 10. As statedabove, improvements in linearity and operating efficiency can beobtained when using a combination of resistive biasing, active biasingand current mirror biasing. This combination of bias schemes cantherefore be used in combination with a linear amplifier to provide alinear amplifier with superior linearity and operating efficiency whencontrasted with known bias schemes.

[0048]FIG. 13 is a schematic diagram illustrating a bias network 1300according to another embodiment of the present invention. The biasnetwork 1300 is similar to the bias network 1000 illustrated in FIG. 10,except the bias voltage source Vbias 1004 is formulated with a pair ofdiode connected transistors 1004 and a series resistor 1302 to generatea desired bias voltage on the integrated circuit (IC) chip. Thoseskilled in the art shall readily appreciate that a desired bias voltagecan also be generated by replacing the pair of diode connectedtransistors 1004 with a single transistor, more than two transistors,one or more diodes, or combinations thereof. More than a single seriesresistor can also be combined with the transistor(s) and/or diode(s) tomore particularly refine the desired bias voltage characteristics. Thebias network 1300 is optionally coupled to ground via an inductor 1304that functions to alter the AC impedance characteristics of the biasnetwork 1300.

[0049] Certain modifications and improvements will occur to thoseskilled in the art upon a reading of the foregoing description. By wayof example, just as the inventive embodiments disclosed herein describespecific combinations of bias networks, different combinations arepossible with reduced, but yet superior performance over classic biasnetworks known in the art. The present invention is also useful incombination with many other types of circuits beyond merely linearamplifiers. Further, the present invention can be constructed usingvarious combinations of the circuit elements, so long as the requisiteresistor(s) and/or inductor(s) are present to tailor the impedance ofthe particular bias network. It should be understood that all suchmodifications and improvements have been deleted herein for the sake ofconciseness and readability but are properly within the scope of thefollowing claims.

We claim:
 1. A linear amplifier bias network comprising: a radio frequency bipolar junction transistor having a collector, emitter and base; a capacitor having one end coupled to the base of the bipolar junction transistor and having an opposite end configured to receive a radio frequency signal; a second bipolar junction transistor having a base, a collector and an emitter, wherein the collector is coupled to a dc supply voltage; a first resistor having one end coupled to the base of the second bipolar junction transistor and having an opposite end coupled to a bias voltage source; and a second resistor having a first end coupled to the emitter and having a second end coupled to the base of the radio frequency bipolar junction transistor, the second resistor having a resistance value rendering the linear amplifier bias network capable of minimizing gain expansion associated with the radio-frequency bipolar junction transistor.
 2. The linear amplifier bias network according to claim 1 further comprising a third resistor having one end coupled to the bias voltage source and having an opposite end coupled to the second end of the second resistor, wherein the second and third resistors are capable of adjusting a bias impedance associated with the bias network such that the bias network can achieve a desired temperature compensation characteristic.
 3. The linear amplifier bias network according to claim 2 further comprising: a ground node; a third bipolar junction transistor having a base, collector and emitter, wherein the emitter of the third bipolar junction transistor is coupled to the ground node; a fourth resistor having one end coupled to the base of the third bipolar junction transistor and having an opposite end coupled to the second end of the second resistor; and a fifth resistor having one end coupled to the collector of the third bipolar junction transistor and having an opposite end coupled to the second end of the second resistor; wherein a combination of resistance values for the first, second, third, fourth and fifth resistors are capable of adjusting a bias impedance associated with the bias network such that the bias network can achieve a desired temperature compensation characteristic and further such that the bias network can achieve a desired level of quiescent current and minimize gain expansion associated with the radio frequency bipolar junction transistor.
 4. The linear amplifier bias network according to claim 3 wherein the bias voltage source comprises a resistor/diode network coupled to a supply voltage to generate a desired supply reference voltage.
 5. The linear amplifier bias network according to claim 3 wherein the bias voltage source comprises: a diode network; and a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the diode network such that a predetermined voltage drop is achieved across the diode network relative to the ground node to produce a desired bias voltage for the linear amplifier bias network.
 6. The linear amplifier bias network according to claim 5 wherein the diode network comprises a plurality of diodes and a series resistor.
 7. The linear amplifier bias network according to claim 3 wherein the bias voltage source comprises: a transistor network configured as a diode network; and a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the transistor network such that a predetermined voltage drop is achieved across the transistor network relative to the ground node to produce a desired supply reference voltage for the linear amplifier bias network.
 8. The linear amplifier bias network according to claim 7 wherein the transistor network comprises a plurality of bipolar junction transistors and a series resistor.
 9. The linear amplifier bias network according to claim 8 further comprising an inductor having a first end coupled to the ground node and further having an opposite end coupled to the emitter of the third bipolar junction transistor such that the emitter of the third bipolar junction transistor is coupled to the ground node solely through the inductor.
 10. The linear amplifier bias network according to claim 9 wherein the emitter of the third bipolar junction transistor is further coupled to the transistor network such that a portion of he transistor network is coupled to the ground node solely through the inductor.
 11. The linear amplifier bias network according to claim 9 wherein any single resistor selected from the group consisting of the first, second, third, fourth and fifth resistors is configured to have zero resistance.
 12. The linear amplifier bias network according to claim 2 further comprising: a ground node; and a third bipolar junction transistor having a base, collector and emitter, wherein the emitter of the third bipolar junction transistor is coupled to the ground node and wherein the base and collector of the third bipolar junction transistor are coupled to the second end of the second resistor.
 13. The linear amplifier bias network according to claim 12 wherein the bias voltage source comprises a resistor/diode network coupled to a supply voltage to generate a desired supply reference voltage.
 14. The linear amplifier bias network according to claim 12 wherein the bias voltage source comprises: a diode network; and a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the diode network such that a predetermined voltage drop is achieved across the diode network relative to the ground node to produce a desired bias voltage for the linear amplifier bias network.
 15. The linear amplifier bias network according to claim 14 wherein the diode network comprises a plurality of diodes and a series resistor.
 16. The linear amplifier bias network according to claim 11 wherein the bias voltage source comprises: a transistor network configured as a diode network; and a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the transistor network such that a predetermined voltage drop is achieved across the transistor network relative to the ground node to produce a desired supply reference voltage for the linear amplifier bias network.
 17. The linear amplifier bias network according to claim 16 wherein the transistor network comprises a plurality of bipolar junction transistors and a series resistor.
 18. The linear amplifier bias network according to claim 17 further comprising an inductor having a first end coupled to the ground node and further having an opposite end coupled to the emitter of the third bipolar junction transistor such that the emitter of the third bipolar junction transistor is coupled to the ground node solely through the inductor.
 19. The linear amplifier bias network according to claim 18 wherein any single resistor selected from the group consisting of the first, second and third resistors is configured to have zero resistance.
 20. The linear amplifier bias network according to claim 18 wherein the emitter of the third bipolar junction transistor is further coupled to the transistor network such that a portion of the transistor network is coupled to the ground node solely through the inductor.
 21. The linear amplifier bias network according to claim 20 wherein any single resistor selected from the group consisting of the first, second and third resistors is configured to have zero resistance.
 22. The linear amplifier bias network according to claim 2 further comprising: a ground node; a third bipolar junction transistor having a base, collector and emitter, wherein the emitter of the third bipolar junction transistor is coupled to the ground node and wherein the collector of the third bipolar junction transistor is coupled to the second end of the second resistor; and a fourth resistor having one end coupled to the base of the third bipolar junction transistor and having an opposite end coupled to the second end of the second resistor, wherein a combination of resistance values for the first, second, third and fourth resistors are capable of adjusting a bias impedance associated with the bias network such that the bias network can achieve a desired temperature compensation characteristic and further such that the bias network can achieve a desired level of quiescent current and minimize gain expansion associated with the radio frequency bipolar junction transistor.
 23. The linear amplifier bias network according to claim 22 wherein the bias voltage source comprises a resistor/diode network coupled to a supply voltage to generate a desired supply reference voltage.
 24. The linear amplifier bias network according to claim 22 wherein the bias voltage source comprises: a diode network; and a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the diode network such that a predetermined voltage drop is achieved across the diode network relative to the ground node to produce a desired bias voltage for the linear amplifier bias network.
 25. The linear amplifier bias network according to claim 24 wherein the diode network comprises a plurality of diodes and a series resistor.
 26. The linear amplifier bias network according to claim 22 wherein the bias voltage source comprises: a transistor network configured as a diode network; and a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the transistor network such that a predetermined voltage drop is achieved across the transistor network relative to the ground node to produce a desired supply reference voltage for the linear amplifier bias network.
 27. The linear amplifier bias network according to claim 26 wherein the transistor network comprises a plurality of bipolar junction transistors and a series resistor.
 28. The linear amplifier bias network according to claim 27 further comprising an inductor having a first end coupled to the ground node and further having an opposite end coupled to the emitter of the third bipolar junction transistor such that the emitter of the third bipolar junction transistor is coupled to the ground node solely through the inductor.
 29. The linear amplifier bias network according to claim 28 wherein any single resistor selected from the group consisting of the first, second, third and fourth resistors is configured to have zero resistance.
 30. The linear amplifier bias network according to claim 28 wherein the emitter of the third bipolar junction transistor is further coupled to the transistor network such that a portion of the transistor network is coupled to the ground node solely through the inductor.
 31. The linear amplifier bias network according to claim 30 wherein any single resistor selected from the group consisting of the first, second, third and fourth resistors is configured to have zero resistance.
 32. The linear amplifier bias network according to claim 2 further comprising: a ground node; a third bipolar junction transistor having a base, collector and emitter, wherein the emitter of the third bipolar junction transistor is coupled to the ground node and wherein the base of the third bipolar junction transistor is coupled to the second end of the second resistor; and a fourth resistor having one end coupled to the collector of the third bipolar junction transistor and having an opposite end coupled to the second end of the second resistor, wherein a combination of resistance values for the first, second, third and fourth resistors are capable of adjusting a bias impedance associated with the bias network such that the bias network can achieve a desired temperature compensation characteristic and further such that the bias network can achieve a desired level of quiescent current and minimize gain expansion associated with the radio frequency bipolar junction transistor.
 33. The linear amplifier bias network according to claim 32 wherein the bias voltage source comprises a resistor/diode network coupled to a supply voltage and configured to generate a desired supply reference voltage.
 34. The linear amplifier bias network according to claim 32 wherein the bias voltage source comprises: a diode network; and a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the diode network such that a predetermined voltage drop is achieved across the diode network relative to the ground node to produce a desired bias voltage for the linear amplifier bias network.
 35. The linear amplifier bias network according to claim 34 wherein the diode network comprises a plurality of diodes and a series resistor.
 36. The linear amplifier bias network according to claim 32 wherein the bias voltage source comprises: a transistor network configured as a diode network; and a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the transistor network such that a predetermined voltage drop is achieved across the transistor network relative to the ground node to produce a desired supply reference voltage for the linear amplifier bias network.
 37. The linear amplifier bias network according to claim 36 wherein the transistor network comprises a plurality of bipolar junction transistors and a series resistor.
 38. The linear amplifier bias network according to claim 37 further comprising an inductor having a first end coupled to the ground node and further having an opposite end coupled to the emitter of the third bipolar junction transistor such that the emitter of the third bipolar junction transistor is coupled to the ground node solely through the inductor.
 39. The linear amplifier bias network according to claim 3 8 wherein any single resistor selected from the group consisting of the first, second, third and fourth resistors is configured to have zero resistance.
 40. The linear amplifier bias network according to claim 38 wherein the emitter of the third bipolar junction transistor is further coupled to the transistor network such that a portion of the transistor network is coupled to the ground node solely through the inductor.
 41. The linear amplifier bias network according to claim 40 wherein any single resistor selected from the group consisting of the first, second, third and fourth resistors is configured to have zero resistance.
 42. A linear amplifier bias network comprising: a radio frequency bipolar junction transistor having a base, collector and emitter; a capacitor having one end coupled to the base of the radio frequency bipolar junction transistor and having an opposite end configured to receive a radio frequency input signal; a second bipolar junction transistor having a base, collector and emitter, wherein the collector of the second bipolar junction transistor is coupled to a dc supply voltage; a first resistor having one end coupled to the base of the second bipolar junction transistor and an opposite end coupled to a bias voltage source; a second resistor having one end coupled to the emitter of the second bipolar junction transistor and having a second end configured to supply a bias current; and a third resistor having one end coupled to the bias voltage source and an opposite end coupled to the second end of the second resistor, wherein a combination of resistance values for the first, second and third resistors render the linear amplifier bias network capable of minimizing gain expansion associated with the radio frequency bipolar junction transistor and further wherein a combination of resistance values for the first, second and third resistors are capable of adjusting a bias impedance associated with the bias network such that the bias network can achieve a desired temperature compensation characteristic and further such that the bias network can achieve a desired level of quiescent current associated with the radio frequency bipolar junction transistor.
 43. The linear amplifier bias network according to claim 42 further comprising: a ground node; a third bipolar junction transistor having a base, collector and emitter, wherein the emitter of the third bipolar junction transistor is coupled to the ground node; a fourth resistor having one end coupled to the base of the third bipolar junction transistor and having an opposite end coupled to the second end of the second resistor; and a fifth resistor having one end coupled to the collector of the third bipolar junction transistor and having an opposite end coupled to the second end of the second resistor; wherein a combination of resistance values for the first, second, third, fourth and fifth resistors are capable of adjusting a bias impedance associated with the bias network such that the bias network can achieve a desired temperature compensation characteristic and further such that the bias network can achieve a desired level of quiescent current associated with the radio frequency bipolar junction transistor.
 44. The linear amplifier bias network according to claim 43 wherein the bias voltage source comprises a resistor/diode network coupled to a supply voltage and configured to generate a desired reference supply voltage.
 45. The linear amplifier bias network according to claim 43 wherein the bias voltage source comprises: a diode network; and a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the diode network such that a predetermined voltage drop is achieved across the diode network relative to the ground node to produce a desired bias voltage for the linear amplifier bias network.
 46. The linear amplifier bias network according to claim 45 wherein the diode network comprises a plurality of diodes and a series resistor.
 47. The linear amplifier bias network according to claim 43 wherein the bias voltage source comprises: a transistor network configured as a diode network; and a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the transistor network such that a predetermined voltage drop is achieved across the transistor network relative to the ground node to produce a desired supply reference voltage for the linear amplifier bias network.
 48. The linear amplifier bias network according to claim 47 wherein the transistor network comprises a plurality of bipolar junction transistors and a series resistor.
 49. The linear amplifier bias network according to claim 48 further comprising an inductor having a first end coupled to the ground node and further having an opposite end coupled to the emitter of the third bipolar junction transistor such that the emitter of the third bipolar junction transistor is coupled to the ground node solely through the inductor.
 50. The linear amplifier bias network according to claim 49 wherein any single resistor selected from the group consisting of the first, second, third, fourth and fifth resistors is configured to have zero resistance.
 51. The linear amplifier bias network according to claim 49 wherein the emitter of the third bipolar junction transistor is further coupled to the transistor network such that a portion of the transistor network is coupled to the ground node solely through the inductor.
 52. The linear amplifier bias network according to claim 51 wherein any single resistor selected from the group consisting of the first, second, third, fourth and fifth resistors is configured to have zero resistance.
 53. A linear amplifier bias network comprising: a radio frequency bipolar junction transistor having a base, collector and emitter; a capacitor having one end coupled to the base of the bipolar junction transistor and having an opposite end configured to receive a radio frequency input signal; a ground node; a second bipolar junction transistor having a base, collector and emitter, wherein the emitter of the second bipolar junction transistor is coupled to the ground node; a first resistor having one end coupled to a bias voltage source and further having a second end coupled to the base of the radio frequency bipolar junction transistor; a second resistor having one end coupled to the base of the second bipolar junction transistor and having an opposite end coupled to the second end of the first resistor; and a third resistor having one end coupled to the collector of the second bipolar junction transistor and having an opposite end coupled to the second end of the first resistor; wherein a combination of resistance values for the first, second and third resistors are capable of adjusting a bias impedance associated with the bias network such that the bias network can achieve a desired temperature compensation characteristic and further such that the bias network can achieve a desired level of quiescent current and minimize gain expansion associated with the radio frequency bipolar junction transistor.
 54. The linear amplifier bias network according to claim 53 further comprising an inductor having a first end coupled to the ground node and further having an opposite end coupled to the emitter of the second bipolar junction transistor such that the emitter of the second bipolar junction transistor is coupled to the ground node solely through the inductor.
 55. The linear amplifier bias network according to claim 54 further comprising: a third bipolar junction transistor having a base, collector and emitter, wherein the collector of the third bipolar junction transistor is coupled to a dc supply voltage; a fourth resistor having a first end coupled to the emitter of the third bipolar junction transistor and having a second end coupled to the second end of the first resistor; and a fifth resistor having a first end coupled to the base of the third bipolar junction transistor and having an opposite end coupled to the bias voltage supply; wherein a combination of resistance values for the first, second, third, fourth and fifth resistors are capable of adjusting a bias impedance associated with the bias network such that the bias network can achieve a desired temperature compensation characteristic and further such that the bias network can achieve a desired level of quiescent current and minimize gain expansion associated with the radio frequency bipolar junction transistor.
 56. The linear amplifier bias network according to claim 55 wherein any single resistor selected from the group consisting of the first, second, third, fourth and fifth resistors is configured to have zero resistance.
 57. The linear amplifier bias network according to claim 54 wherein the bias voltage source comprises a resistor/diode network coupled to a supply voltage and configured to generate a desired reference supply voltage.
 58. The linear amplifier bias network according to claim 54 wherein the bias voltage source comprises: a diode network having a first node and a second node; and a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the diode network first node such that a predetermined voltage drop is achieved across the diode network relative to the ground node to produce a desired bias voltage for the linear amplifier bias network.
 59. The linear amplifier bias network according to claim 58 wherein the diode network includes at least one series resistor.
 60. The linear amplifier bias network according to claim 59 further comprising an inductor having a first end coupled to the ground node and further having an opposite end coupled to the diode network such that a portion of the diode network is coupled to the ground node solely through the inductor.
 61. The linear amplifier bias network according to claim 60 wherein any single resistor selected from the group consisting of the first, second and third resistors is configured to have zero resistance.
 62. The linear amplifier bias network according to claim 54 wherein the bias voltage source comprises: a transistor network configured as a diode network; and a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the transistor network such that a predetermined voltage drop is achieved across the transistor network relative to the ground node to produce a desired supply reference voltage for the linear amplifier bias network.
 63. The linear amplifier bias network according to claim 62 wherein the transistor network includes a series resistor.
 64. The linear amplifier bias network according to claim 63 further comprising an inductor having a first end coupled to the ground node and further having an opposite end coupled to the transistor network such that a portion of the transistor network is coupled to the ground node solely through the inductor.
 65. The linear amplifier bias network according to claim 64 wherein any single resistor selected from the group consisting of the first, second and third resistors is configured to have zero resistance.
 66. A linear amplifier bias network comprising: a radio frequency bipolar junction transistor having a base, collector and emitter; a capacitor having one end coupled to the base of the radio frequency bipolar junction transistor and having an opposite end configured to receive a radio frequency input signal; a ground node; a second bipolar junction transistor having a base, collector and emitter, wherein the base of the second bipolar junction transistor is coupled to the collector of the second bipolar junction transistor and further wherein the base of the second bipolar junction transistor is coupled to the base of the radio frequency bipolar junction transistor; a first resistor having one end coupled to a bias voltage source and having a second end coupled to the collector of the second bipolar junction transistor; and a first inductor having one end coupled to the emitter of the second bipolar junction transistor and having an opposite end coupled to the ground node; wherein a combination of impedance values for the first resistor and the first inductor is capable of adjusting a bias impedance associated with the bias network such that the bias network can achieve a desired temperature compensation characteristic and further such that the bias network can achieve a desired level of quiescent current associated with the radio frequency bipolar junction transistor.
 67. The linear amplifier bias network according to claim 66 further comprising: a third bipolar junction transistor having a base, collector and emitter, wherein the collector of the third bipolar junction transistor is coupled to a dc supply voltage; a second resistor having one end coupled to the base of the third bipolar junction transistor and having an opposite end coupled to the bias voltage supply; and a third resistor having one end coupled to the emitter of the third bipolar junction transistor and having an opposite end coupled to the collector of the second bipolar junction transistor, wherein a combination of impedance values for the inductor and resistance values for the first, second and third resistors are capable of adjusting a bias impedance associated with the bias network such that the bias network can achieve a desired temperature compensation characteristic and further such that the bias network can achieve a desired level of quiescent current associated with the radio frequency bipolar junction transistor.
 68. The linear amplifier bias network according to claim 67 wherein any single resistor selected from the group consisting of the first, second and third resistors is configured to have zero resistance.
 69. The linear amplifier bias network according to claim 66 wherein the bias voltage source comprises a resistor/diode network coupled to a supply voltage and configured to generate a desired reference supply voltage.
 70. The linear amplifier bias network according to claim 66 wherein the bias voltage source comprises: a diode network; and a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the diode network such that a predetermined voltage drop is achieved across the diode network relative to the ground node to produce a desired bias voltage for the linear amplifier bias network.
 71. The linear amplifier bias network according to claim 70 wherein the diode network includes a series resistor.
 72. The linear amplifier bias network according to claim 71 further comprising a second inductor having a first end coupled to the ground node and further having an opposite end coupled to the diode network such that a portion of the diode network is coupled to the ground node solely through the second inductor.
 73. The linear amplifier bias network according to claim 71 wherein the diode network is coupled to the first inductor such that a portion of the diode network is coupled to the ground node solely through the first inductor.
 74. The linear amplifier bias network according to claim 66 wherein the bias voltage source comprises: a transistor network configured as a diode network; and a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the transistor network such that a predetermined voltage drop is achieved across the transistor network relative to the ground node to produce a desired supply reference voltage for the linear amplifier bias network.
 75. The linear amplifier bias network according to claim 74 wherein the transistor network comprises a plurality of bipolar junction transistors and a series resistor.
 76. The linear amplifier bias network according to claim 75 further comprising a second inductor having a first end coupled to the ground node and further having an opposite end coupled to the transistor network such that a portion of the transistor network is coupled to the ground node solely through the second inductor.
 77. The linear amplifier bias network according to claim 75 wherein the transistor network is coupled to the first inductor such that a portion of the transistor network is coupled to the ground node solely through the first inductor.
 78. A linear amplifier bias network comprising: a radio frequency bipolar junction transistor having a base, collector and emitter; a capacitor having one end coupled to the base of the radio frequency bipolar junction transistor and having an opposite end configured to receive a radio frequency input signal; a buffered passive bias network having a first bipolar junction transistor and further having an emitter resistor associated with the first bipolar junction transistor; and a current mirror bias network coupled to the buffered passive bias network, the current mirror bias network having a second bipolar junction transistor and further having a collector resistor and a base resistor associated with the second bipolar junction transistor; wherein a combination of resistance values for the emitter, base and collector resistors are capable of adjusting a bias impedance associated with the bias network such that the bias network can achieve a desired temperature compensation characteristic and further such that the bias network can achieve a desired level of quiescent current and minimize gain expansion associated with the radio frequency bipolar junction transistor.
 79. The linear amplifier bias network according to claim 78 further comprising an inductor having a first end coupled to a ground node and further having an opposite end coupled to the emitter of the second bipolar junction transistor such that the emitter of the second bipolar junction transistor is coupled to the ground node solely through the inductor.
 80. The linear amplifier bias network according to claim 79 wherein any single resistor selected from the group consisting of the emitter resistor, the collector resistor and the base resistor is configured to have zero resistance.
 81. The linear amplifier bias network according to claim 78 further comprising: a supply voltage node; a ground node; a diode network; and a resistor having a first end coupled to the supply voltage node and having an opposite end coupled to the diode network such that a predetermined voltage drop is achieved across the diode network relative to the ground node to produce a desired bias voltage for the linear amplifier bias network.
 82. The linear amplifier bias network according to claim 81 wherein the diode network includes a plurality of diodes and a series resistor.
 83. The linear amplifier bias network according to claim 82 further comprising an inductor having a first end coupled to the ground node and further having an opposite end coupled to the diode network such that a portion of the diode network is coupled to the ground node solely through the inductor.
 84. The linear amplifier bias network according to claim 83 wherein any single resistor selected from the group consisting of the emitter resistor, the collector resistor and the base resistor is configured to have zero resistance.
 85. The linear amplifier bias network according to claim 78 further comprising: a supply voltage node; a ground node; a transistor network configured as a diode network; and a resistor having a first end coupled to the supply voltage node and having an opposite end coupled to the transistor network such that a predetermined voltage drop is achieved across the transistor network relative to the ground node to produce a desired bias voltage for the linear amplifier bias network.
 86. The linear amplifier bias network according to claim 85 wherein the transistor network includes a plurality of bipolar junction transistors and a series resistor.
 87. The linear amplifier bias network according to claim 86 further comprising an inductor having a first end coupled to the ground node and further having an opposite end coupled to the transistor network such that a portion of the transistor network is coupled to the ground node solely through the inductor.
 88. The linear amplifier bias network according to claim 87 wherein any single resistor selected from the group consisting of the emitter resistor, the collector resistor and the base resistor is configured to have zero resistance.
 89. A linear amplifier bias network comprising: a radio frequency bipolar junction transistor having a base, collector and emitter; a capacitor having one end coupled to the base of the radio frequency bipolar junction transistor and having an opposite end configured to receive a radio frequency input signal; a buffered passive bias network having a first bipolar junction transistor and further having at least one emitter resistor associated with the first bipolar junction transistor; and a current mirror bias network coupled to the buffered passive bias network, the current mirror bias network having a second bipolar junction transistor and further having at least one emitter inductor associated with the second bipolar junction transistor; wherein a combination of impedance values for the at least one emitter resistor and at least one emitter inductor are capable of adjusting a bias impedance associated with the bias network such that the bias network can achieve a desired temperature compensation characteristic and further such that the bias network can achieve a desired level of quiescent current associated with the radio frequency bipolar junction transistor.
 90. A linear amplifier bias network comprising: a radio frequency bipolar junction transistor having a base, collector and emitter; a capacitor having a first end coupled to the base of the radio frequency bipolar junction transistor and having an opposite end configured to receive a radio frequency input signal; an active bias network having a first bipolar junction transistor and a base resistor; and means for establishing an impedance in the emitter leg of the first bipolar junction transistor to achieve a desired level of quiescent bias current associated with the radio frequency bipolar junction transistor, wherein the means for establishing the impedance is independent of the base resistor.
 91. The linear amplifier bias network according to claim 90 further comprising first means for establishing an impedance for the linear amplifier bias network to achieve a desired first temperature compensation characteristic wherein the first means for establishing an impedance for the linear amplifier bias network is independent of the means for establishing an impedance in the emitter leg of the first bipolar junction transistor and is further independent of the base resistor.
 92. The linear amplifier bias network according to claim 91 further comprising second means for establishing an impedance for the linear amplifier bias network to achieve a desired second temperature compensation characteristic wherein the second means for establishing an impedance for the linear amplifier bias network is independent of the first means and the means for establishing an impedance in the emitter leg of the first bipolar junction transistor and is further independent of the base resistor.
 93. The linear amplifier bias network according to claim 92 wherein the second means comprises a bipolar junction transistor having a base, a collector and an emitter, and further comprising an inductor having a first end coupled to the emitter of the bipolar junction transistor and having an opposite end coupled to a ground node.
 94. A method of producing a desired temperature compensation characteristic associated with a linear amplifier bias network comprising the steps of: providing a radio frequency bipolar junction transistor having a base, collector and emitter; providing a capacitor having a first end coupled to the base of the radio frequency bipolar junction transistor and further having an opposite end configured to receive a radio frequency input signal; providing an active bias network having a first bipolar junction transistor and a base resistor associated therewith; providing an emitter resistor associated with the first bipolar junction transistor; and adjusting the resistance of the emitter resistor to achieve a desired temperature compensation characteristic for the radio frequency bipolar junction transistor.
 95. The method of claim 94 further comprising the step of modifying the active bias network with a second resistor to produce a buffered passive bias network.
 96. The method of claim 95 further comprising the step of adjusting the resistance of the second resistor and the emitter resistor to achieve a desired impedance for the buffered passive bias network and further to achieve a desired level of quiescent bias current for the radio frequency bipolar junction transistor.
 97. The method of claim 96 further comprising the step of coupling a current mirror bias network to the buffered passive bias network.
 98. The method of claim 97 further comprising the step of adjusting the impedance of the current mirror bias network and the buffered passive bias network in combination to achieve a desired temperature compensation characteristic for the linear amplifier bias network and further to achieve a desired quiescent bias current for the radio frequency bipolar junction transistor. 